Chung-Chin Lu: Difference between revisions
Protrait |
m added Category:Academia using HotCat |
||
| (7 intermediate revisions by one other user not shown) | |||
| Line 1: | Line 1: | ||
{{People | {{People | ||
|portrait = cclu_photo.jpg | |||
|caricature=Chung-Chin LuComing1.jpg | |caricature=Chung-Chin LuComing1.jpg | ||
|organization=National Tsing Hua University | |organization=National Tsing Hua University | ||
| Line 6: | Line 7: | ||
|region=Asia | |region=Asia | ||
|country=Taiwan | |country=Taiwan | ||
|stakeholdergroup= | |stakeholdergroup= | ||
|email=cclu@ee.nthu.edu.tw | |email=cclu@ee.nthu.edu.tw | ||
|Protrait=}} | |Protrait=}} | ||
| Line 18: | Line 18: | ||
* Visiting Scholar, Inst. for Neural Computation, University of California San Diego (2007 - 2008) | * Visiting Scholar, Inst. for Neural Computation, University of California San Diego (2007 - 2008) | ||
* | * Chairman, EE Dept, NTHU (2003 - 2006) | ||
* | * Vice Chairman, EE Dept, NTHU (2000 - 2003) | ||
* Visiting Scholar, EE Dept, Princeton University, USA (1998 - 1999) | * Visiting Scholar, EE Dept, Princeton University, USA (1998 - 1999) | ||
* Associate Professor, EE Dept, NTHU (1987 - 2000) | * Associate Professor, EE Dept, NTHU (1987 - 2000) | ||
==ICANN and Internet Governance Participation== | ==ICANN and Internet Governance Participation== | ||
* Convenor, Civil IoT Construction Program Task Force, 2017 – Present | |||
* Co-chair, 2006 Fall Workshop on Information Theory and Communications and 2006 Taiwan-Hong Kong Joint Workshop on Information Theory and Communications, 2006 | * Co-chair, 2006 Fall Workshop on Information Theory and Communications and 2006 Taiwan-Hong Kong Joint Workshop on Information Theory and Communications, 2006 | ||
| Line 33: | Line 33: | ||
==Education== | ==Education== | ||
* | * PhD in Electrical Engineering, University of Southern California | ||
* M. Sc, Electrical Engineering, University of Southern California | * M. Sc, Electrical Engineering, University of Southern California | ||
* | * B. Sc, Electrical Engineering, National Taiwan University | ||
| Line 65: | Line 64: | ||
==Awards== | ==Awards== | ||
[[Category:Academia]] | |||
Latest revision as of 20:43, 6 July 2021
 |
|
| Organization: | National Tsing Hua University |
| Region: | Asia |
| Country: | Taiwan |
| Email: | cclu@ee.nthu.edu.tw |
Chung-Chin Lu is a professor from the Department of Electrical Engineering at National Tsing Hua University in Taiwan. His research interests include communication theory, system bioinformatics, quantum information science, and error-correcting codes.
Career History
- Professor, Dept of Electrical Engineering, National Tsing Hua University (2000 - Present)
- Visiting Scientist, Computational Neurobiology Lab, Salk Institute, USA (2007 - 2008)
- Visiting Scholar, Inst. for Neural Computation, University of California San Diego (2007 - 2008)
- Chairman, EE Dept, NTHU (2003 - 2006)
- Vice Chairman, EE Dept, NTHU (2000 - 2003)
- Visiting Scholar, EE Dept, Princeton University, USA (1998 - 1999)
- Associate Professor, EE Dept, NTHU (1987 - 2000)
ICANN and Internet Governance Participation
- Convenor, Civil IoT Construction Program Task Force, 2017 – Present
- Co-chair, 2006 Fall Workshop on Information Theory and Communications and 2006 Taiwan-Hong Kong Joint Workshop on Information Theory and Communications, 2006
- Program Co-chair, International Symposium on Communications, 1997
- Program Co-chair, Workshop on Communication networks, 1996
Education
- PhD in Electrical Engineering, University of Southern California
- M. Sc, Electrical Engineering, University of Southern California
- B. Sc, Electrical Engineering, National Taiwan University
Publications
Chung-Chin Lu is the author and co-author of many publications:
- On bit-level trellis complexity of Reed-Muller codes
- A search of minimal key functions for normal basis multipliers
- A systolic array implementation of the Feng-Rao algorithm
- Loss behavior in space priority queue with batch Markovian arrival process-Discrete-time case
- Efficient architectures for syndrome generation and error location search in the decoding of Hermitian codes
- A serial-in-serial-out hardware architecture for systematic encoding of Hermitian codes via Groebner bases
- Prediction of splice sites with dependency graphs and their expanded Bayesian networks
- Space-time code design for CPFSK modulation over frequency-nonselective fading channels
- Systolic array implementation of a real-time symbol-optimum multiuser detection algorithm
- A view of Gaussian elimination applied to early stopped Berlekamp-Massey algorithm
- Extracting transcription factor binding sites from unaligned gene sequences with statistical models