22
edits
Changes
→Career History: resume editing
==Career History==
==Career History==
Dept of Electrical Engineering, National Tsing Hua University (2008 - Present)
Dept of Electrical Engineering, National Tsing Hua University (2008 - Present)
Computational Neurobiology Lab, Salk Institute, USA (2007 - 2008)
Computational Neurobiology Lab, Salk Institute, USA (2007 - 2008)
Inst. for Neural Computation, University of California San Diego (2007 - 2008)
Inst. for Neural Computation, University of California San Diego (2007 - 2008)
EE Dept, Princeton University (1998 - 1999)
EE Dept, Princeton University (1998 - 1999)
==ICANN and Internet Governance Participation==
==ICANN and Internet Governance Participation==
Co-chair, Workshop on Information Theory and Communications and 2006 Taiwan-Hong Kong Joint Workshop on Information Theory and Communications, 2006
Co-chair, Workshop on Information Theory and Communications and 2006 Taiwan-Hong Kong Joint Workshop on Information Theory and Communications, 2006
Program Co-chair, International Symposium on Communications, 1997
Program Co-chair, International Symposium on Communications, 1997
Program Co-chair, Workshop on Communication networks, 1996
Program Co-chair, Workshop on Communication networks, 1996
==Education==
==Education==
B. Sc, Electrical Engineering, National Taiwan University
B. Sc, Electrical Engineering, National Taiwan University
M. Sc, Electrical Engineering, University of Southern California
M. Sc, Electrical Engineering, University of Southern California
PhD in Electrical Engineering, University of Southern California
PhD in Electrical Engineering, University of Southern California
==Publications==
==Publications==
Chung-Chin Lu is the author and co-author of many publications:
Chung-Chin Lu is the author and co-author of many publications:
On bit-level trellis complexity of Reed-Muller codes
On bit-level trellis complexity of Reed-Muller codes
A search of minimal key functions for normal basis multipliers
A search of minimal key functions for normal basis multipliers
A systolic array implementation of the Feng-Rao algorithm
A systolic array implementation of the Feng-Rao algorithm
Loss behavior in space priority queue with batch Markovian arrival process-Discrete-time case
Loss behavior in space priority queue with batch Markovian arrival process-Discrete-time case
Efficient architectures for syndrome generation and error location search in the decoding of Hermitian codes
Efficient architectures for syndrome generation and error location search in the decoding of Hermitian codes
A serial-in-serial-out hardware architecture for systematic encoding of Hermitian codes via Groebner bases
A serial-in-serial-out hardware architecture for systematic encoding of Hermitian codes via Groebner bases
Prediction of splice sites with dependency graphs and their expanded Bayesian networks
Prediction of splice sites with dependency graphs and their expanded Bayesian networks
Space-time code design for CPFSK modulation over frequency-nonselective fading channels
Space-time code design for CPFSK modulation over frequency-nonselective fading channels
Systolic array implementation of a real-time symbol-optimum multiuser detection algorithm
Systolic array implementation of a real-time symbol-optimum multiuser detection algorithm
A view of Gaussian elimination applied to early stopped Berlekamp-Massey algorithm
A view of Gaussian elimination applied to early stopped Berlekamp-Massey algorithm
Extracting transcription factor binding sites from unaligned gene sequences with statistical models
Extracting transcription factor binding sites from unaligned gene sequences with statistical models
==Awards==
==Awards==